Slurry and manufacturing semiconductor using the slurry

ABSTRACT

The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

BACKGROUND

In the production processes for semiconductor devices, a polishingprocess is carried out to subject a surface of a wafer to aplanarization. A polishing process can be applied to different materialsof surfaces of the wafer multiple times during different stages offabrication processing of a semiconductor device. In the process ofchemical mechanical polishing, the wafer is mounted to a rotating plate,and a surface of the wafer is brought into contact with a pad of apolishing machine. Rotating the rotating plate and the pad of thepolishing machine while a slurry is supplied. That is, a slurry flowsbetween the wafer surface and the pad, and polishing of the wafersurface is achieved as a result of the mechanical friction caused by thepolishing particles in the slurry and the protrusions at the surface ofthe pad.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flow chart of a method for planarizing a metal-dielectricsurface according to various aspects of one or more embodiments of thepresent disclosure.

FIG. 2 to FIG. 3 are schematic cross sectional views at variousoperations of a method for planarizing a metal-dielectric surfaceaccording to one or more embodiments of the present disclosure.

FIG. 4 and FIG. 5 are schematic diagrams showing interaction betweenceria compounds and a surface of silicon dioxide according to one ormore embodiments of the present disclosure.

FIG. 6 is a flow chart of a method for planarizing a metal-dielectricsurface according to various aspects of one or more embodiments of thepresent disclosure.

FIG. 7 is a schematic cross sectional view at one of various operationsof a method for planarizing a metal-dielectric surface according to oneor more embodiments of the present disclosure.

FIG. 8 is a flow chart of a method for manufacturing a semiconductoraccording to various aspects of one or more embodiments of the presentdisclosure.

FIG. 9 to FIG. 16 are schematic cross sectional views at variousoperations of a method for manufacturing a semiconductor according toone or more embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As used herein, the terms such as “first,” “second” and “third” describevarious elements, components, regions, layers and/or sections, theseelements, components, regions, layers and/or sections should not belimited by these terms. These terms may be only used to distinguish oneelement, component, region, layer or section from another. The termssuch as “first,” “second” and “third” when used herein do not imply asequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forththe broad scope of the disclosure are approximations, the numericalvalues set forth in the specific examples are reported as precisely aspossible. Any numerical value, however, inherently contains certainerrors necessarily resulting from the standard deviation found in therespective testing measurements. Also, as used herein, the term “about”generally means within 10%, 5%, 1%, or 0.5% of a given value or range.Alternatively, the term “about” means within an acceptable standarderror of the mean when considered by one of ordinary skill in the art.Other than in the operating/working examples, or unless otherwiseexpressly specified, all of the numerical ranges, amounts, values andpercentages such as those for quantities of materials, durations oftimes, temperatures, operating conditions, ratios of amounts, and thelikes thereof disclosed herein should be understood as modified in allinstances by the term “about.” Accordingly, unless indicated to thecontrary, the numerical parameters set forth in the present disclosureand attached claims are approximations that can vary as desired. At thevery least, each numerical parameter should at least be construed inlight of the number of reported significant digits and by applyingordinary rounding techniques. Ranges can be expressed herein as from oneendpoint to another endpoint or between two endpoints. All rangesdisclosed herein are inclusive of the endpoints, unless specifiedotherwise.

A chemical mechanical polish (CMP) operation is commonly used in variousstages of a semiconductor manufacturing process. As for advanced processof semiconductor manufacturing, a metal material is applied in formationof a contact to a source/drain region of a transistor. A slurry used inthe CMP operation includes abrasives for the purpose of mechanical forceincrement. Considering high hardness of metal material, a slurry havinga high hardness of abrasive as its advantages in high removal rate tometal material by mechanical force is used when the removal target ismetal material in the CMP operation. In order to control CMP operation,a stop layer is applied for detection of termination of the CMPoperation. A stop layer ideally should have high selectivity to thetarget material under a predetermined slurry. However, it is difficultto have high selectivity between the target layer and the stop layerunder a condition of high mechanical force being applied.

For example, SiO₂, SiN and Si are widely used as hard mask for waferpatterning to enhance patterning precision. For more delicate and tinierpatterns, novel candidate such as transition metal oxide (e.g., HfO₂,ZrO₂, Y₂O₃, TiO₂, Al₂O₃, Ta₂O₅, La₂O₃, etc.) were introduced to enhanceetch rate selectivity. By introducing transition metal oxide, higheraspect ratio with less mask loss can be achieved. However, transitionmetal oxide is hard to act as a stopping layer during CMP process. Thisdisadvantage will lead to unwanted thickness loss during the CMP processand make such process more difficult to control. Without chelatingagent, polishing driving force of traditional SiO₂ abrasive totransition metal oxide is mainly mechanical.

Present disclosure provides a CMP slurry utilizing a new abrasive toreplace traditional SiO₂ abrasive in metal CMP operations so as toeffectively suppress (transition) metal oxide removal rate whilemaintain the removal rate for other materials during the metal CMPoperations. In some embodiments, Ceria oxide (CeO_(x)) is utilized asthe new abrasive for metal CMP operations. Compared to traditional SiO₂abrasive, Ceria oxide (CeO_(x)) possesses lower Mohs hardness and higherweight density. Consequently, lower abrasive content (in weight percent)and thus less mechanical force is applied the substance to be removed.On the other hand, the chemical force possessed by the Ceria oxide(CeO_(x)) provides another channel for planarization which is morematerial-specific. The reduction of the mechanical force and enhancementof chemical force allow Ceria oxide (CeO_(x)) to be a desired candidateto effectively suppress (transition) metal oxide removal rate whilemaintain the removal rate for other materials during the metal CMPoperations.

Some embodiments of the present disclosure provide a slurry used in achemical mechanical polish (CMP) operation for planarizing ametal-dielectric surface. The slurry includes an abrasive, a removalrate regulator and a buffering agent. The abrasive includes a ceriacompound, which has a Mohs hardness less than that of silicon dioxide.The removal rate regulator is to adjust removal rates of the slurry tometal and to dielectric material, and the buffering agent is to adjust apH value of the slurry. The slurry provided by some embodiments of thepresent disclosure includes a dielectric material removal rate higherthan a metal oxide removal rate. The slurry provided by some embodimentsof the present disclosure includes a metal removal rate higher than themetal oxide removal rate. The slurry provided by some embodiments of thepresent disclosure is suitable for CMP operation targeting to a surfaceincluding a portion of pure metal and a portion of silicon oxide, andthe CMP operation stops at a metal oxide layer.

As shown in FIG. 1, some embodiments of the present disclosure provide amethod M10 for planarizing a metal-dielectric surface, e.g. of asemiconductor substrate. The method M10 includes: (O11) providing aslurry to a metal-dielectric surface, wherein the first metal-dielectricsurface includes a silicon oxide portion and a metal portion, and theslurry comprises a ceria compound; and (O12) performing a chemicalmechanical polish (CMP) operation using the slurry to simultaneouslyremove the silicon oxide portion and the metal portion.

For further illustrating the method M10, FIG. 2 is cross sectionalperspective of a substrate 10 in accordance with some embodiments of thepresent disclosure. The method M10 is applied to the semiconductor asshown in FIG. 2. The substrate 10 including at least a semiconductor fin101, at least a source/drain region 102, and at least a gate structure103 is provided. Referring to FIG. 2, the cross sectional perspectivealong the semiconductor fin 101 of such embodiments shows a plurality ofsource/drain regions 102 and a plurality of gate structures 103 over thesemiconductor fin 101. The source/drain regions 102 are at leastpartially disposed in the semiconductor fin 101, and the gate structures103 are disposed over the semiconductor fin 101 and adjacent to thesource/drain regions 102. The gate structures 103 are over and incontact with the semiconductor fin 101, and between two adjacentsource/drain regions 102. In some embodiments, each of the gatestructures 103 has a longitudinal direction perpendicular to alongitudinal direction of the semiconductor fin 101. In order words,each of the gate structures 103 is disposed across the semiconductor fin101, and the semiconductor fin 101 is perpendicular to each of the gatestructures 103 from a top view perspective (not shown).

The gate structures 103 can be metal gate structures in some embodimentsof the present disclosure. In some embodiments, the gate structure 103includes a metal gate electrode, a gate oxide, a pair of spacers, and anitride contact. For example, the gate oxide is between the gateelectrode and the semiconductor fin 101, the nitride contact is over thegate electrode, and the spacers are disposed on lateral sidewalls of thestack of the gate oxide, the gate electrode and the nitride contact.Details of the gate structure 103 are omitted herein. Different types ofgate structures can be applied, and it is not limited herein. Shapes andconfigurations of the gate structures 103 can be adjusted depending ondifferent applications. FIG. 2 is for illustration of relative positionsof the semiconductor fin 101, the source/drain regions 102, and the gatestructures 103 according to some embodiments from a cross sectionperspective, but not intended to limit the present disclosure.

A plurality of portions of a metal oxide layer 104 is formed on the gatestructures 103 individually. A dielectric layer 105 is formed over thesemiconductor fin 101, the source/drain regions 102, the gate structures103 and the metal oxide layer 104. A metal layer 106 is formed fillingbetween the gate structures 103, between the portions of the metal oxidelayer 104, and over the metal oxide layer 104. A metal-dielectricsurface S1 is exposed and targeted to a CMP operation. In accordancewith (O11) of the method M10, in some embodiments of the presentdisclosure, the dielectric layer 105 is silicon oxide, and themetal-dielectric surface S1 includes a silicon oxide portion of thedielectric layer 105 and a metal portion of the metal layer 106. Aslurry includes a ceria compound as an abrasive is provided.

In accordance with (O12) of the method M10, a CMP operation is performedusing the slurry to simultaneously remove the silicon portion and themetal portion. As shown in FIG. 3, a portion of the metal layer 106 anda portion of the dielectric layer 105 are removed, and the CMP operationstops at the metal oxide layer 104 over the gate structures 103. In someembodiments, the slurry has a dielectric material removal rate higherthan a metal oxide removal rate. In some embodiments, the slurry has ametal removal rate higher than the metal oxide removal rate. In someembodiments, the slurry has a removal rate selectivity of dielectricmaterial to metal oxide greater than 30. In some embodiments, the slurryhas a removal rate selectivity of metal to metal oxide greater than 30.

In some embodiments of the present disclosure, the metal oxide layer 104is formed over the gate structure 103 by a deposition operation. In someembodiments, the metal oxide layer 104 includes at least one ofzirconium dioxide (ZrO₂), hafnium zirconium oxide (HfZrO_(x)), hafniumsilicon oxide (HfSiO_(x)), hafnium silicon oxynitride (HfSiON),zirconium silicon oxide (ZrSiO_(x)), hafnium zirconium silicon oxide(HfZrSiO_(x)), aluminum oxide (Al₂O₃), hafnium aluminum oxide(HfAlO_(x)), hafnium aluminum nitride (HfAlN_(x)), zirconium aluminumoxide (ZrAlO_(x)), lanthanum oxide (La₂O₃), titanium dioxide (TiO₂),ytterbium(III) oxide (Yb₂O₃), yttrium(III) oxide (Y₂O₃), hafnium oxide(HfO₂) and tantalum pentoxide (Ta₂O₅), and x is a positive integer.

In some embodiments of the present disclosure, the dielectric layer iscomposed of non-metallic dielectric material. The dielectric layerincludes at least one of silicon dioxide (SiO₂), silicon nitride (SiN),boron nitride (BN), germanium nitride (GeN), silicon carbonitride(SiCN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON),silicon oxycarbide (SiOC).

In some embodiments of the present disclosure, the metal layer includespure metal and alloy. Pure metal is selected from one of tungsten (W),cobalt (Co), ruthenium (Ru), copper (Cu), and alloy includes at leastone of tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu).

In some embodiments of the present disclosure, the removal rateregulator is selected from a group of organic acid and ammonia. Theorganic acid includes amino acid and other types of organic acid. Insome embodiments, the removal rate regulator is selected from a group ofammonia, amino acid, and other organic acid (besides amino acid). Whenthe organic acid is other than amino acid, the organic acid has afunctional group of R—COOH and has a molar mass in a range of 2000 and8000 g/mol, wherein R represents a carbon chain. The removal rateregulator can be a metal removal rate enhancer or a barrier removal rateenhancer. In some embodiments, the metal removal rate enhancer is usedto adjust the metal removal rate of the slurry by increase chemicalforce of the slurry to the metal layer 106 in order to balance anetching selectivity of metal to dielectric material of the slurry. Insome embodiments, the barrier removal rate enhancer is used to adjustthe dielectric removal rate of the slurry by increase chemical force ofthe slurry to the dielectric layer 105 in order to balance an etchingselectivity of metal to dielectric material of the slurry. In someembodiments, a difference between the dielectric removal rate and themetal removal rate of the slurry can be less than 100 angstrom/minute.

In some embodiments of the present disclosure, the buffering agentincludes at least one of citric acid, acetic acid and potassiumdihydrogen phosphate (KH₂PO₄). The buffering agent is added to adjust apH value of the slurry to be suitable for a suitable CMP condition inaccordance with materials of the metal layer 106, dielectric layer 105and the metal oxide layer 104. In some embodiments, the buffering agenthas a weight percentage less than 1 wt % to the slurry. In someembodiments, the pH value of the slurry is in a range of 5 to 12. Insome embodiments, the pH value of the slurry is greater than 7.

In some embodiments of the present disclosure, the abrasives consist ofceria compounds. In some embodiments, the ceria compounds of theabrasives include at least one of ceric dioxide (CeO₂), cerium trioxide(Ce₂O₃), ceric hydroxide (Ce(OH)₄), cerium-nitride, cerium-fluoride andcerium-sulfide. The ceria compounds have a Mohs hardness less than 7, orless than a Mohs hardness of silicon dioxide abrasives. However, theceria compounds as the abrasives of the slurry can provide good CMPresult due to chemical characteristics of the ceria compounds to thehydroxyl group on the surface of the dielectric layer 105 in aqueousmedium.

As for suitable abrasives of a slurry in a CMP operation targeting to ametal-dielectric surface, ceria compounds can be in nanocrystals, havinga Mohs hardness less than 7, and good dispersion property but notdissolvable in water. More importantly, ceria compounds provide chemicalforce in removal of the dielectric layer 105 via the illustration inFIG. 4 and FIG. 5 of present disclosure.

The dielectric layer 105 being silicon dioxide for illustration, asshown in FIG. 4, an interaction between silicon dioxide and Ce⁴⁺ underaqueous condition enhances removal rate of the slurry to the dielectriclayer 105. Referring to FIG. 4, a ceria cation reacts with the hydroxylgroup on the surface of the dielectric layer 105 under aqueous conditionto form Si(OH)₄ (silicic acid). The hydroxyl groups can be generated onthe ceria surface by dissociation reaction of H₂O on defect site or byprotonation of outermost oxygens of the surface. Ceria is functionalizedwith the hydroxyl groups in aqueous medium. Interactions between ceriacompounds and the hydroxyl groups on the dielectric layer 105, and alsointeractions between hydroxyl groups and positive silicon of thedielectric layer 105 facilitate removal rate of the slurry to thedielectric layer 105.

Referring to FIG. 5, due to reactions between the ceria compounds andthe surface of silicon dioxide of the dielectric layer 105, during andat the end of CMP operation, the ceria compounds can be found on thesurface of the dielectric layer 105. Ceria compounds in nanocrystal formcan be observed by top-view electron microscopy inspection. Ceriacompounds may also be identified by Energy-Dispersive X-ray Spectroscopy(EDX) mapping by showing ceria signals at the as-polished surface of thedielectric layer 105. A post-CMP cleaning operation can be optionallyperformed to remove the ceria compounds on the surface of the dielectriclayer 105.

In some embodiments of the present disclosure, the CMP operation stopsat an exposure of the metal oxide layer 104. As shown in FIG. 3, ametal-dielectric surface S2 is provided as the exposure of the metaloxide layer 104. In some embodiments, the metal-dielectric surface S2includes a metal oxide portion of the metal oxide layer 104 and a metalportion of the metal layer 106. In some embodiments, themetal-dielectric surface S2 includes a metal oxide portion of the metaloxide layer 104, a metal portion of the metal layer 106 and a dielectricportion of the dielectric layer 105.

In some embodiments of the present disclosure, the CMP operation removesa portion of the metal oxide layer 104 before the CMP operation isterminated. As shown in FIG. 6 to FIG. 7, the CMP operation iscontinuously performed on the metal-dielectric surface S2 using the sameslurry as to the metal-dielectric surface S1. A portion of the metaloxide layer 104 in thickness is removed. And the method 10 may furtherinclude: (O13) providing a slurry to another metal-dielectric surface,wherein the metal-dielectric surface includes a metal oxide portion anda metal portion; and (O14) performing a CMP operation using the slurryto simultaneously remove the metal oxide portion and the metal portion.However due to high selectivity between the metal oxide layer 104 andthe metal layer 106, the removed portion of the metal oxide layer 104 inthickness can be very limited. Loss of the metal oxide layer 104 and athickness of the metal layer 106 between the gate structures 103 (thethickness of the metal layer 106 is measured from a top of the metallayer 106 away from the semiconductor fin 101 to a bottom of the metallayer 106 in contact with the semiconductor fin 101) can be controlled.

For ease of understanding, various CMP operations for planarizing ametal-dielectric surface of different embodiments of the presentdisclosure are provided. And a method for manufacturing a semiconductorincluding a CMP operation using the above illustrated slurry is providedaccording to different embodiments of the present disclosure. Suchembodiments are for illustration of effectiveness and advantages ofslurries provided different embodiments of the present disclosure, butit is not intended to limit the present disclosure to specificembodiments.

As shown in FIG. 8, some embodiments of the present disclosure provide amethod M20 for manufacturing a semiconductor. The method M20 includes:(O21) receiving a substrate, having a fin structure, a plurality ofsource/drain regions in the fin structures, a plurality of gatestructures over the fin structure and adjacent to the source/drainregions from a cross sectional perspective; (O22) forming a metal oxidelayer over the gate structures; (O23) forming a dielectric layer overthe metal oxide layer; (O24) forming a metal layer over the metal oxidelayer; and (O25) performing a chemical mechanical polish (CMP) operationto remove a portion of the dielectric layer and a portion of the metallayer, wherein a slurry used in the CMP operation comprises a ceriacompound.

FIG. 9 is in accordance with some embodiments of the present disclosurefor illustration of the method M20. In accordance with In accordancewith (O21) of the method M20, the substrate 10 including at least asemiconductor fin 101, at least a source/drain region 102, and at leasta continuous gate structure 103′ is provided. Referring to FIG. 9, thecross sectional perspective of such embodiments shows a plurality ofsource/drain regions 102 formed in the semiconductor fin 101. Thesource/drain regions 102 are at least partially disposed in thesemiconductor fin 101, and the continuous gate structures 103′ aredisposed over the semiconductor fin 101 and adjacent to the source/drainregions 102. The continuous gate structures 103′ are over and in contactwith the semiconductor fin 101. The continuous gate structures 103′ canincludes a plurality of metal gate structures 1031 and a plurality ofisolations 1032. In some embodiments of the present disclosure, theisolations 1032 are composed of dielectric material and intervallydisposed between the metal gate structures 1031. The metal gatestructures 1031 can be similar to the metal gate structures 103 as shownin FIG. 2 to FIG. 3, and repeating description is omitted herein. Themetal gate structures 1031 can be formed by using technologies of polydummy gate formation. Details of formation of the metal gate structures1031 are omitted herein. The isolations 1032 are made of dielectricmaterials, which can have similar properties to that of the dielectriclayer 105 as illustrated above.

In some embodiments of the present disclosure, the source/drain regions102 can be epitaxial structures, e.g. SiP (silicon epitaxy with in-situP doping), SiGe (silicon germanium) or Ge (germanium). In someembodiments, the source/drain regions 102 can be formed by removing aportion of the semiconductor fin 101 and epitaxially growing crystals inthe recessed portion of the semiconductor fin 101. In some embodiments,the source/drain regions 102 are formed after formation of the gatestructures 103, and the source/drain regions 102 are formed between twoadjacent gate structures 103. Shapes and configurations of the pluralityof source/drain regions 102 can be different depending on applications.And shapes and configurations of different source/drains 102 can be alsodifferent. In some embodiments, the source/drain regions 102 areprotruded from a top surface S101 of the semiconductor fin 101 dependingon formations of the source/drain regions 102, and at a same level ofelevation, the source/drain regions 10 are disposed intervally betweenthe gate structures 103 over the semiconductor fin 101. FIG. 9 is forillustration of relative positions of the semiconductor fin 101, thesource/drain regions 102, and the continuous gate structure 103′ onlybut not intended to limit the present disclosure.

Referring to FIG. 10 to FIG. 11 and in accordance with (O22) of themethod M20, a metal oxide layer 104 is formed over the continuous gatestructure 103′ by, for example, a deposition operation. The metal oxidelayer 104 is continuously disposed over the continuous gate structure103′, covering the metal gate structures 1031 and the isolations 1032.Portions of the metal oxide layer 104 over the isolations 1032 of thecontinuous gate structure 103′ are removed, and a plurality of remainedportions of the metal oxide layer 104 is formed as shown in FIG. 11. Theremained portions of metal oxide layer 104 cover the metal gatestructures 1031.

Referring to FIG. 12 and in accordance with (O23) of the method M20, adielectric layer 105 is formed over the remained portions of the metaloxide layer 104. The dielectric layer 105 covers the semiconductor fin101, the source/drain regions 102, the metal gate structures 1031 andthe metal oxide layer 104.

Referring to FIG. 13, prior to formation of a metal layer 106 inaccordance with (O24) of the method M20, a portion of the dielectriclayer 105 over the metal oxide layer 104 and between the remainedportions of the metal oxide layer 104 over the isolations 1032 areremoved. In some embodiments of the present disclosure, material of theisolations 1032 and that of the dielectric layer 105 are the same. Insome embodiments of the present disclosure as shown in FIG. 13, theisolations 1032 between the metal gate structures 1031 are removedconcurrently in the operation of removal of the portion of thedielectric layer 105. The isolations 1032 are removed to form a layer ofgate structures 103 including a plurality of metal gate structures 1031.The source/drain regions 102 are exposed from the gate structures 103,the metal oxide layer 104 and the dielectric layer 105.

Referring to FIG. 14 and in accordance with (O24) of the method M20, themetal layer 106 is formed over the metal oxide layer 104. The metallayer 106 also fills between the gate structures 103, where theisolations 1032 was disposed, and between the remained portions of themetal oxide layer 104 as well. The metal layer 106 is disposed adjacentto the dielectric layer 105. A metal-dielectric surface S1 is exposed,wherein the first metal-dielectric surface S1 includes a metal portionof the metal layer 106 and a dielectric portion of the dielectric layer105.

Referring to FIG. 15 and in accordance with (O25) of the method M20, themetal-dielectric surface S1 is targeted to a CMP operation. The CMPoperation is performed to remove a portion of the metal layer 106 and aportion of the dielectric layer 105 simultaneously, wherein the slurryused in the CMP operation includes a ceria compound. The slurry usedherein is similar to the slurry as illustrate above in method M10 andFIG. 1 to FIG. 8, and redundant description is omitted herein for thepurpose brevity.

In some embodiments of the present disclosure, the CMP operation stopsat an exposure of the metal oxide layer 104, wherein a metal-dielectricsurface S2 is provided. The metal-dielectric surface S2 includes a metaloxide portion of the metal oxide layer 104 and a metal portion of themetal layer 106, and optionally a dielectric portion of the dielectriclayer 105. In some embodiments, the CMP operation removes a portion ofthe metal oxide layer 104 before the CMP operation is terminated asshown in FIG. 16. The CMP operation is continuously performed on themetal-dielectric surface S2 using the same slurry as to themetal-dielectric surface S1. However, similar to the mechanism of theslurry removal rates to metal, dielectric and metal oxide materials, theremoved portion of the metal oxide in thickness can be very limited dueto high selectivity between the metal oxide layer 104 and the metallayer 106. Loss of the metal oxide layer 104 and a thickness of themetal layer 106 between the gate structures 103 can be controlled.

Table 1 provides different embodiments of the present disclosure ofdifferent slurries, the slurries of the embodiments are provided to thesemiconductors with the same structures as shown in FIG. 14 under sameCMP conditions. Wherein the metal layer 106 is cobalt (Co), the metaloxide layer 104 is zirconium dioxide (ZrO₂), and the dielectric layer105 is silicon dioxide (SiO₂). In the embodiments listed in Table 1, theabrasive is ceria dioxide (CeO₂), the removal rate regulator is anorganic acid having a molar mass of 5000 g/mol, and the buffering agentis citric acid.

TABLE 1 Embodiment Condition 1 2 3 4 5 6 pH value 9.5 9 8.5 9 9.5 9.5CeO₂ 0.25 0.15 0.10 0.05 0.10 0.05 (wt % to slurry) Removal rate 0.600.48 0.48 0.48 0.60 0 regulator (wt % to slurry) Buffering agent <0.1<0.1 <0.1 <0.1 <0.1 <0.1 (wt % to slurry) SiO₂ removal 435 460 140 80630 250 rate (A/min) Co removal 373 300 150 520 430 32 rate (A/min) ZrO₂removal <1 <1 <1 2 <1 1 rate (A/min)

As shown in Embodiment 1 to Embodiment 6 in the Table 1 above, in someembodiments of the present disclosure, the ceria compounds of theabrasives have a weight percentage in a range from 0.05 wt % to 0.25 wt% to the slurry to achieve desired removal rates with respect tosubstances to be removed. In some embodiments of the present disclosure,the slurry has a removal rate selectivity of the metal to the metaloxide greater than 30 (e.g. the minimum selectivity ratio Co/ZrO₂ amongthe 6 embodiments is 32, as shown in the Embodiment 6). In someembodiments of the present disclosure, the slurry has a removal rateselectivity of the dielectric material to the metal oxide greater than30 (e.g. the minimum selectivity ratio SiO₂/ZrO₂ of the 6 embodiments is40, as shown in the Embodiment 4). In some embodiments of the presentdisclosure, a pH value is controlled to be greater than 7 to achievedesired removal rates with respect to substances to be removed. In someembodiments of the present disclosure, the buffering agent is less than1 wt % to the slurry. Therefore, some embodiments of the presentdisclosure provide a slurry including ceria compounds as abrasives issuitable for polishing a metal-dielectric surface. The slurry has verylimited removal rate to the metal oxide materials, and loss metal oxidelayer 104 can be reduced.

Some embodiments of the present disclosure provide a slurry. The slurryincludes an abrasive including a ceria compound; a removal rateregulator to adjust removal rates of the slurry to metal and todielectric material; and a buffering agent to adjust a pH value of theslurry, wherein the slurry comprises a dielectric material removal ratehigher than a metal oxide removal rate.

Some embodiments of the present disclosure provide a method formanufacturing a semiconductor. The method includes: receiving asubstrate having a semiconductor fin, a source/drain region in thesemiconductor fin, and a gate structure over the semiconductor fin andadjacent to the source/drain region from a cross sectional perspective;forming a metal oxide layer over the gate structure; forming adielectric layer over the metal oxide layer; forming a metal layer overthe metal oxide layer; and performing a chemical mechanical polish (CMP)operation to remove a portion of the dielectric layer and a portion ofthe metal layer, wherein a slurry used in the CMP operation comprises aceria compound.

Some embodiments of the present disclosure provide a method forplanarizing a metal-dielectric surface. The method includes: providing aslurry to a first metal-dielectric surface, wherein the firstmetal-dielectric surface comprises a silicon oxide portion and a metalportion, and wherein the slurry comprises a ceria compound; andperforming a chemical mechanical polish (CMP) operation using the slurryto simultaneously remove the silicon oxide portion and the metalportion.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method for manufacturing a semiconductor,comprising: receiving a substrate having a semiconductor fin, asource/drain region in the semiconductor fin, and a gate structure overthe semiconductor fin and adjacent to the source/drain region from across sectional perspective; forming a metal oxide layer over the gatestructure; forming a dielectric layer over the metal oxide layer;forming a metal layer over the metal oxide layer; and performing achemical mechanical polish (CMP) operation to remove a portion of thedielectric layer and a portion of the metal layer, the CMP operationstopping at the metal oxide layer, wherein a slurry used in the CMPoperation comprises a ceria compound.
 2. The method of claim 1, whereina weight percentage of the ceria compound in the slurry is in a rangefrom 0.05 wt % to 0.25 wt %.
 3. The method of claim 1, wherein theslurry further includes a removal rate regulator to adjust removal ratesof the slurry to the metal layer and to the dielectric layer.
 4. Themethod of claim 1, wherein the slurry has a dielectric material removalrate higher than a metal oxide removal rate.
 5. The method of claim 1,wherein the metal layer is adjacent to the dielectric layer and fillingbetween the gate structures.
 6. A method for planarizing ametal-dielectric surface, comprising: receiving a substrate having afirst metal-dielectric surface, wherein a dielectric portion and a metalportion are exposed at the first metal-dielectric surface; providing aslurry to the first metal-dielectric surface, wherein the slurrycomprises a ceria compound; and performing a chemical mechanical polish(CMP) operation using the slurry to simultaneously remove the dielectricportion and the metal portion.
 7. The method of claim 6, wherein asecond metal-dielectric surface is generated after the CMP operation,and the ceria compound is over the second metal-dielectric surface afterthe CMP operation.
 8. The method of claim 7, wherein the ceria compoundover the second metal-dielectric surface of the substrate is removed toby a post-CMP cleaning operation.
 9. The method of claim 6, furthercomprising: providing the slurry to a second metal-dielectric surface,wherein the second metal-dielectric surface comprises a metal oxideportion and the metal portion; and performing a CMP operation using theslurry to simultaneously remove the metal oxide portion and the metalportion, wherein a removal rate to the metal oxide portion issubstantially slower than a removal rate to the metal portion.
 10. Themethod of claim 9, wherein the slurry has a removal rate selectivity ofthe dielectric portion to the metal oxide portion greater than
 30. 11.The method of claim 6, wherein the slurry further comprises: a removalregulator to adjust removal rates of the slurry to the metal portion andthe dielectric portion; and a buffering agent to adjust a PH value ofthe slurry.
 12. The method of claim 11, wherein the removal rateregulator is selected from a group of ammonia, amino acid and otherorganic acid.
 13. The method of claim 11, wherein the buffering agentincludes at least one of citric acid, acetic acid and potassiumdihydrogen phosphate (KH₂PO₄).
 14. The method of claim 1, wherein theceria compound includes at least one of ceric dioxide (CeO₂), ceriumtrioxide (Ce₂O₃), ceric hydroxide (Ce(OH)₄), cerium-nitride,cerium-fluoride and cerium-sulfide.
 15. The method of claim 1, whereinthe metal layer includes pure metal and alloy, the pure metal isselected from one of tungsten (W), cobalt (Co), ruthenium (Ru), copper(Cu), and alloy includes at least one of tungsten (W), cobalt (Co),ruthenium (Ru), copper (Cu).
 16. The method of claim 1, wherein themetal oxide layer includes at least one of zirconium dioxide (ZrO₂),hafnium zirconium oxide (HfZrO_(x)), hafnium silicon oxide (HfSiO_(x)),hafnium silicon oxynitride (HfSiON), zirconium silicon oxide(ZrSiO_(x)), hafnium zirconium silicon oxide (HfZrSiO_(x)), aluminumoxide (Al₂O₃), hafnium aluminum oxide (HfAlO_(x)), hafnium aluminumnitride (HfAlN_(x)), zirconium aluminum oxide (ZrAlO_(x)), lanthanumoxide (La₂O₃), titanium dioxide (TiO₂), ytterbium(III) oxide (Yb₂O₃),yttrium(III) oxide (Y₂O₃), hafnium oxide (HfO₂) and tantalum pentoxide(Ta₂O₅), and x is a positive integer.
 17. The method of claim 1, whereinthe dielectric layer includes at least one of silicon dioxide (SiO₂),silicon nitride (SiN), boron nitride (BN), germanium nitride (GeN),silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), siliconoxynitride (SiON), silicon oxycarbide (SiOC).
 18. A method formanufacturing a semiconductor, comprising: receiving a semiconductorsubstrate, comprising a plurality of metal gate structures and aplurality of isolations disposed between the plurality of metal gatestructures respectively, wherein a top surface of the plurality of metalgate structures and a top surface of the plurality of isolations areexposed; forming a metal oxide layer over the top surface of theplurality of metal gate structures and the top surface of the pluralityof isolations; removing portions of the metal oxide layer to expose thetop surface of the plurality of isolations; forming a dielectric layerover and between the metal oxide layer; removing a portion of thedielectric layer to expose the plurality of isolations; removing theplurality of isolations; forming a metal layer over between theplurality of gate structures, between the metal oxide layer, andsurrounded by the dielectric layer; performing a planarization operationto remove a portion of the dielectric layer and a portion of the metallayer until an exposure of the metal oxide layer, wherein a slurry usedin the planarization operation comprises a ceria compound, and the ceriacompound in the slurry bonds to oxygens in the dielectric layer andattached to a planarized surface of the dielectric layer after theplanarization operation.
 19. The method of claim 18, wherein the slurryhas a removal rate selectivity of the metal layer to the metal oxidelayer greater than
 30. 20. The method of claim 18, wherein a pH value ofthe slurry is in a range of from 5 to 12.